The present invention relates generally to communication systems, and more specifically, to a system and method for reducing power consumption in a Low Density Parity-Check (LDPC) Decoder.
For efficient data transmission in a communication system, data transmission rates should be as close as possible to a theoretical Shannon limit. The Shannon limit of a communication channel is defined as the maximum amount of error-free digital information that can be transmitted with a specified bandwidth in the presence of noise interference. Currently used error-correcting codes in communication systems, such as forward error-correcting (FEC) codes and cyclic redundancy codes (CRC), are used to provide data transmission rates that are close to the Shannon limit. FEC codes differ from CRC in that FEC codes are specially designed to enable the receiver to correct errors in each received message independently, rather than wait for a large number of messages to arrive before performing the error-correction. Therefore, FEC codes enable seamless data transmission. Currently, LDPC codes are being used for performing FEC.
Communication systems that utilize LDPC codes for FEC use an LDPC decoder to decode incoming bits. An LDPC decoder has multiple bit nodes and check nodes and receives an independent message bit at each bit node. The value of a message bit is checked against a check bit at a check node, and the correct value of the message bit is updated at the bit node. The correct value of the message bit is resolved in an iterative exchange of messages between the bit nodes and the check nodes. The updating procedure is a major factor in dynamic power consumption in an LDPC decoder. In other words, a reduction in dynamic power consumption is linearly related to the number of check nodes that need to be updated. In wireless standards such as WiMax/WiBro, 802.11n, DVB-S2 and 10 Gbase-T, power consumption during the decoding operation is a matter of concern.
LDPC decoders currently used in communication systems keep updating check nodes and bit nodes for each iteration of an exchange of a message, even if their corresponding message value has been resolved or matured to a reasonable extent. This results in unnecessary updating of stable check nodes and bit nodes, causing increased dynamic power consumption. Some communication systems using LDPC decoders propose a bit node gating scheme to reduce dynamic power consumption. In this scheme, a bit node is turned OFF if the value of the incoming message bit has been resolved or matured at the bit node. In trellis topology, it is difficult to design the clock-gating circuit for turning off multiple bit nodes because the process requires a significant number of memory blocks in the design. Moreover, turning OFF a stable bit node only eliminates the procedure of updating the bit node, but the bit node is still read and the Check Node update process is still carried out during forward-error correction, resulting in unnecessary power consumption. It would be advantageous to be able to reduce dynamic power consumption in an LDPC decoder.